1. Field of the Invention
The present invention relates to a microcomputer having a register file formed by a built-in RAM and consisting of a plurality of register banks and, more particularly, to speeding up data transfer of a plurality of registers between register banks.
2. Description of the Prior Art
In most microcomputers having a large number of registers, a register file is formed by registers which are constituted by a RAM. In addition, the registers are divided into a plurality of groups (register banks) to store each state of the microcomputer so that high-speed context switching is made possible by shifting the register banks.
FIG.7 is a block diagram of the key parts of a conventional microcomputer comprising a register file formed by a plurality of register banks. In this example, the microcomputer comprises sixteen register banks, each consisting of eight 32-bit general-purpose registers, totalling 128 registers. In the figure, reference numeral 1 represents a register section in which registers are used to form a register file, 2 a control section for outputting to the register section 1 the register address of a register to be accessed and a signal for controlling the register section 1 so as to control the whole microcomputer, 3 an internal data bus as the passage of data between blocks in the microcomputer, 4 and 5 temporary registers disposed between an arithmetic logic section 6 and the internal bus 3, and 6 an arithmetic logic section for inputting data outputted to the internal data bus 3 through the temporary registers 4 and 5, executing various operations and outputting results to the internal data bus 3.
FIG. 8 is a block diagram of the internal configuration of the register section 1 shown in FIG. 7. In the figure, reference numerals 7(0)-7(31) represent an array of memory cells, 8 a decoder for decoding n number of high-order bits of a register address so as to activate one of the word lines 12(0)-12(31), 9 a decoder for decoding m number of low-order bits of a register address so as to activate one of the signal lines 11(0)-11(31), 10(0)-10(31) selectors for connecting to the internal data bus 3 pairs of bit lines 13(0)-13(31) corresponding to the activated signal line 11(0)-11(31), 11(0)-11(31) a signal line to which the result of decoding by the decoder 9 is outputted, 12(0)-12(31) lines to which the result of decoding by the decoder 8 is outputted, 13(0)-13(31) of bit lines consisting of bit and inverted bit signal lines and intersecting the word lines 12(0)-12(31), 14 a register address signal line to which n number of high-order bits of a register address are inputted, and 15 a register address signal line to which m number of low-order bits of a register address are inputted.
Here, n and m are integers larger than 0 which satisfy the equation 2.sup.n .times.2.sup.m =128, and are set properly by the hardware implementation method. The memory cell arrays 7 correspond to bits 0 to 31 of the 32-bit register from the left, and the memory cell array 7 corresponding to bit N is connected to an N-th data signal line of the internal data bus 3 through the respective selector 10. In other words, each register is formed by the memory cell arrays 7 corresponding to bits 0 to 31, and each register bank consists of eight registers per word line according to the value of n.
FIG.9 is a block diagram of the internal configuration of each memory cell array 7 shown in FIG. 8. In the figure, reference numeral 16 represents a memory cell disposed at a point of intersection between each word line 12 and each bit line 13 for storing one-bit information, and 17 a p-channel complementary metal oxide film semiconductor transistor (abbreviated as p-channel MOST hereinafter) for precharging each bit line 13.
FIG. 10 is a circuit diagram of each memory cell 16 shown in FIG. 9. In the figure, reference numeral 18 are n-channel MOSTs, and 19 inverters for storing one-bit information by being electrically disconnected from the bit line 13 by the n-channel MOST 18 and whose input and output are mutually connected.
Data read and write operations in the register section 1 of the prior art will be described in conjunction with FIGS. 7 to 10.
A data read operation will first be described. The p-channel MOSTs 17 of each memory cell array 7 are turned on for a certain period of time in response to a control signal inputted from the control section 2 so as to precharge all the bit lines 13. Thereafter, n number of high-order bits of a register address inputted from the control section 2 are inputted into the decoder 8, whereby one of the 2.sup.n word lines 12 is activated. Then, the n-channel MOSTs 18 of all the memory cells 16 connected to the activated word line 12 are turned on, and data stored in the memory cells 16 appear on the bit lines 13. Meanwhile, m number of low-order bits of a register address inputted from the control section 2 are inputted into the decoder 9, whereby one of the 2.sup.m signal lines 11 is activated. The bit lines 13 of the memory cell arrays 7 connected to the activated signal line are connected to the internal data bus 3 by the selector 10, and data is outputted to the internal data bus 3.
A data write operation will be described next. The p-channel MOSTs 17 of each memory cell array 7 are turned on for a certain period of time in response to a control signal inputted from the control section 2 so as to precharge all the bit lines 13. Thereafter, m number of low-order bits of a register address inputted from the control section 2 are inputted into the decoder 9, whereby one of the 2.sup.m signal lines 11 is activated. The bit lines 13 of the memory cell arrays 7 connected to the activated signal line are connected to the internal data bus 3 so that data over the internal data bus 3 appears on the bit lines 13 selected by the selector 10. Meanwhile, n number of high-order bits of a register address inputted from the control section 2 are inputted into the decoder 8, whereby one of the 2.sup.n word lines 12 is activated, and the n-channel MOSTs 18 of all the memory cells 16 connected to the activated word line 12 are turned on. Then, data over the bit lines 13 is written on the memory cells 16 connected to the bit lines 13 selected by the selector, and values stored in the memory cells 16 connected to the bit lines 13 not selected by the selector 10 remain unchanged.
Next, the operation of data transfer of a plurality of registers between register banks in the prior art will be described with reference to FIG. 7. The operation will be outlined hereafter. For data transfer between registers, the contents of a source register are read in the temporary register 4, and then are written on a destination register through the arithmetic logic section 6. This process is repeated as many times as the number of registers constituting one register bank (eight times in this case) to complete data transfer of a plurality of registers between register banks.
The i-th and j-th register banks are represented by Ri and Rj, and k-th registers belonging to i-th and j-th register banks are represented by Rik and Rjk (i, j=0-15, k=0-7), respectively. Take the case when data is transferred from the register bank Ri to the register bank Rj. When the register address of the register Rik and a control signal are inputted from the control section 2 to the register section 1, the register section 1 outputs the contents of the register Rik to the internal data bus 3 for storage in the temporary register 4. Thereafter, the contents of the temporary register 5 are cleared. Then, the arithmetic logic section 6 performs a logic sum operation on the temporary registers 4 and 5, and outputs the result of the operation to the register section 1 through the internal data bus 3. At the same time, the register address of the register Rjk and a control signal are also inputted into the register section 1 from the control section 2, and the result of the operation by the arithmetic logic section 6, that is, the contents of the register Rik, are written on the register Rjk. This operation is repeated eight times for register addresses Ri0 to Ri7 to be read and register addresses Rj0 to Rj7 to be written. This repetition completes data transfer from the register bank Ri to the register bank Rj.
Since the conventional microcomputer having a register file consisting of a plurality of register banks and formed by a built-in RAM is structured as described above, for data transfer of a plurality of registers between register banks, the operation of reading and transferring the contents of a source register to a temporary register and then writing them on a destination register needs to be repeated as many times as the number of registers constituting a register bank, thus taking a long time to transfer data.